1. Field of the Invention
The present invention relates to the memory cell array of a non-volatile semiconductor memory device. More particularly, the invention relates to a semiconductor memory device in which the resistance of its source line can be reduced, and the method of manufacturing the same device.
2. Description of the Prior Art
Conventionally, a flash memory device has been known as a semiconductor memory device, particularly as a non-volatile semiconductor memory device having the feature of holding data memorized therein even if the power supply is cut off. Recently, there have arisen both a demand for the increase of a memory capacity by high integration to the flash memory device as well as to other semiconductor devices, and a demand for cost reduction by the reduction of a chip area conflicting with the above trend. In order to respond the demands, the reduction of the area of the memory cell per bit has become absolutely necessary.
Among the memory cells of the flash memory are several types of memory cells, NOR type, AND type, and NAND type memory cells. In the most typical NOR type memory cell, it is known that a stack gate structure is suitable for reducing the area of the memory cell. Hereinafter, the structure of the NOR type memory cell array having the stack gate structure will be shortly described.
FIG. 21 is a block diagram showing the peripheral parts of the memory cell array of the flash memory in a conventional semiconductor memory device. In FIG. 21 are disposed control logic circuit 101, address buffer 102, input-output buffer 103, X address decoder 104, Y address decoder 105, write circuit 106, sense amplifier 107, Y gate 108, and memory cell array 109.
X address decoder 104 selecting a X address to the memory cells of memory cell array 109 flatly arranged in a matrix state is disposed at the position adjacent to memory cell array 109, and Y address decoder 105 selecting a Y address thereto is connected with memory cell array 109 through Y gate 108. When write operation and read operation to the memory cell are done, the addresses of X and Y are selected by control logic circuit 101.
FIG. 22 is a schematic diagram showing the memory cell array of the flash memory in the conventional semiconductor memory. In FIG. 22, because the same reference numerals indicate the same or equivalent parts in FIG. 21, the explanation is omitted. In the figure are disposed source line 110, word lines WLnxe2x88x921, . . . , WLn+2 of X address decoder 104, bit lines BLnxe2x88x922, . . . , BLn+2 of Y gate 108, and source lines SLnxe2x88x921, . . . , SLn+1.
The source lines and the word lines are arranged in the direction of X, and the bit lines are arranged in the direction of Y such that the bit lines cross the source lines and the word lines. The cells disposed in the direction of the word line use a common word line, which is generally formed of such wiring material as polysilicon and the like in the stack gate structure. The common word line is referred to as a control gate because the word line controls the write operation and the read operation of the memory cell. The control gate is elongated in the direction of X on a floating gate serving as the charge storage electrode of each memory cell. The memory cells arranged in the direction of the bit line also use a common bit line, which uses aluminum as the wiring material and is connected with the drain of the memory cell through a contact. The source lines arranged parallel to the word lines are connected with each other at the end of memory cell array 109, and all of the source lines existing in memory cell array 109 use a common source line.
The operation will next be described.
When a specific bit in memory cell array 109 is selected; a voltage is applied between bit line BLn and word line WLn for instance; and a bit in which bit line BLn and word line WLn cross each other is selected, because a current flows from bit line BLn into the bit when the threshold voltage Vth of the selected bit is low (xe2x80x980xe2x80x99 state), a channel current flows from the drain of the selected bit into the source, and finally reaches source line 110 serving as GND. On the other hand, when threshold voltage Vth of the selected bit is high (xe2x80x981xe2x80x99 state), because the channel of the bit does not turn on even if a voltage is applied between bit line BLn and word line WLn, a current does not flow.
Sense amplifier 107 discriminates whether a current flows into the selected bit when a voltage is applied to the bit line. That is, sense amplifier 107 discriminates whether the current flowing into the selected bit is more or less than a certain specific current value. Thereby, information memorized in the selected bit can be read by xe2x80x980xe2x80x99 or xe2x80x981xe2x80x99. However, because the flowing current reduces when the resistance of the source line is high, the possibility that sense amplifier 107 misreads the information memorized in the selected bit increases.
FIG. 23 is a plan view showing the memory cell array of the flash memory in the conventional semiconductor memory device. In FIG. 23 are disposed word line 111, source line 112, floating gate 113, control gate 114, drain 115, and memory cell 116 per bit.
FIGS. 24-27 are sectional views of specific parts in the plan view of the memory cell array shown in FIG. 23. FIG. 24 is a sectional view taken along the line A-Axe2x80x2 in the part of the control gate. FIG. 25 is a sectional view taken along the line B-Bxe2x80x2 in the part of the source line. FIG. 26 is a sectional view taken along the line C-Cxe2x80x2 in the part of the memory cell. FIG. 27 is a sectional view taken along the line D-Dxe2x80x2 in the part of a STI isolation oxide film. In FIGS. 24-27, because the same reference numerals indicate the same or equivalent parts in FIG. 23, the explanation is omitted. From FIG. 25, it can be easily understood that source line 112 has a structure in which the source resistance increases easily in vertical part 121.
STI (Shallow Trench Isolation) isolation oxide film method is a method of forming an isolation oxide film by means of the steps of: selectively etching the part in a semiconductor substrate becoming an isolation oxide film, burying an isolation oxide film in the etched part, and planarizing the surface by means of CMP (Chemical, Mechanical, and Polishing) method and the like. The method is a manufacturing method having been used for the high integration in recent years. Conventionally, a selective oxidation method such as well-known LOCOS method has been used as a method of forming the isolation oxide film.
By the way, there is SAS (Self Aligned Source) structure technology serving as a technology of reducing the area of the memory cell of the flash memory. The SAS structure technology is a technology contrived for the measures against the following drawback. That is, when the isolation oxide film is formed in the source line of the above-described memory cell, a bird""s beak area has become a hindrance to the reduction of the memory cell area though the isolation oxide film has been previously arranged such that the oxide film is not formed in the area serving as the source line. The SAS structure technology is the technology of forming the source line in the following manner. When an isolation oxide film is formed, a stripe-shaped isolation oxide film is formed in the direction of the bit line. After forming the control gate and the floating gate of the memory cell, a part of isolation oxide film formed in the area becoming a source line in a self alignment manner by using the control gate as a part of the mask is removed by means of etching process, and simultaneously the source line is formed by means of ion implantation process.
The conventional semiconductor memory device is arranged as mentioned above. For this reason, in the case the isolation oxide film formed by means of the STI technology is etched by means of the SAS technology when the STI technology is used in combination with the SAS technology, because injection ion species required for sufficiently reducing the source line resistance are not injected, in the ion implantation that is the post process, into a vertical part from which the STI oxide film is removed because of the convexo-concave surface shape of the semiconductor substrate, the source line resistance increases, and thereby the operation in which the channel current of the memory cell appears to be lowered is caused when a cell far from the part in which the source line is drawn is read. As a result, there is a drawback that the sense amplifier apparently determines the threshold voltage of the memory cell to be higher than its actual threshold voltage.
Additionally, in the conventional semiconductor memory device, because the sense amplifier seemingly judges that the threshold voltage of the memory cell is higher than the actual threshold voltage, there is a drawback that discrepancies occur in the write/delete operation because of the increase of the width of distribution of the threshold voltage.
Moreover, in the conventional semiconductor memory device, there is a drawback that the memory cell array malfunctions when the resistance of the source line increases to be shorted.
The present invention has been accomplished to solve the above-mentioned drawbacks, and an object of the present invention is to provide a semiconductor memory device in which a memory cell can be further down-sized by having a structure reducing source line resistance and a method of manufacturing the memory device.
According to a first aspect of the present invention, there is provided a semiconductor memory device including: a plurality of trench parts in a stripe shape formed on a semiconductor; a gate electrode formed to be orthogonal to these trench parts and having longitudinal sides along the orthogonal direction; a first diffused layer formed on the surface of the trench parts and on the semiconductor substrate between the trench parts adjacent to each other along one of the longitudinal sides; a salicide layer formed on the surface of the first diffused layer; and a plurality of second diffused layer formed between the trenches on the other of the longitudinal sides.
Thus, it is possible to achieve easily the reduction of the resistance of the first diffused layer, and also to narrow the width of the diffused layer due to the reduced resistance of the first diffused layer, thereby reducing the area of the memory cell.
Here, the first diffused layer is formed consecutively on the sides and the bottom surfaces of the trench parts, and on the surfaces of the semiconductor substrate between the trench parts, and is formed to the inside of the semiconductor substrate from the salicide layer.
Thus, a junction leakage between the salicide layer and the semiconductor substrate may be suppressed.